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Low Cost Instrumentation Amplifier AD622
FEATURES
Easy to use Low cost solution Higher performance than two or three op amp design Unity gain with no external resistor Optional gains with one external resistor (Gain range: 2 to 1000) Wide power supply range: 2.6 V to 15 V Available in 8-lead PDIP and 8-lead SOIC_N packages Low power, 1.5 mA maximum supply current DC performance 0.15% gain accuracy: G = 1 125 V maximum input offset voltage 1.0 V/C maximum input offset drift 5 nA maximum input bias current 66 dB minimum common-mode rejection ratio: G = 1 Noise 12 nV/Hz @ 1 kHz input voltage noise 0.60 V p-p noise: 0.1 Hz to 10 Hz, G = 10 AC characteristics 800 kHz bandwidth: G = 10 10 s settling time to 0.1% @ G = 1 to 100 1.2 V/s slew rate
PIN CONFIGURATION
RG 1 -IN 2 +IN 3 -VS 4
AD622
8 7 6 5
RG +VS
00777-001
OUTPUT REF
Figure 1. 8-Lead PDIP and 8-Lead SOIC_N (N and R Suffixes)
GENERAL DESCRIPTION
The AD622 is a low cost, moderately accurate instrumentation amplifier that requires only one external resistor to set any gain between 2 and 1000. For a gain of 1, no external resistor is required. The AD622 is a complete difference or subtracter amplifier system that also provides superior linearity and common-mode rejection by incorporating precision lasertrimmed resistors. The AD622 replaces low cost, discrete, two or three op amp instrumentation amplifier designs and offers good commonmode rejection, superior linearity, temperature stability, reliability, and board area consumption. The low cost of the AD622 eliminates the need to design discrete instrumentation amplifiers to meet stringent cost targets. While providing a lower cost solution, it also provides performance and space improvements.
APPLICATIONS
Transducer interface Low cost thermocouple amplifier Industrial process controls Difference amplifier Low cost data acquisition
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)1996-2007 Analog Devices, Inc. All rights reserved.
AD622 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Pin Configuration............................................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Typical Performance Characteristics ............................................. 6 Theory of Operation .........................................................................9 Make vs. Buy: A Typical Application Error Budget..................9 Gain Selection ................................................................................. 11 Input and Output Offset Voltage.............................................. 11 Reference Terminal .................................................................... 11 Input Protection ......................................................................... 11 RF Interference ........................................................................... 11 Ground Returns for Input Bias Currents ................................ 12 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 14
REVISION HISTORY
8/07--Rev. C to Rev. D Updated Format..................................................................Universal Added Thermal Resistance Section ............................................... 5 Added Figure 16................................................................................ 9 Added Large Input Voltages at Large Gains Section.................. 11 Replaced RF Interference Section ................................................ 11 Deleted Grounding Section........................................................... 10 Deleted Figure 16............................................................................ 10 Changes to Ground Returns for Input Bias Currents Section.. 12 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 4/99--Rev. B to Rev. C 8/98--Rev. A to Rev. B 2/97--Rev. 0 to Rev. A 1/96--Revision 0: Initial Version
Rev. D | Page 2 of 16
AD622 SPECIFICATIONS
TA = 25C, VS = 15 V, and RL = 2 k typical, unless otherwise noted. Table 1.
Parameter GAIN Gain Range Gain Error 1 G=1 G = 10 G = 100 G = 1000 Nonlinearity G = 1 to 1000 G = 1 to 100 Gain vs. Temperature VOLTAGE OFFSET Input Offset, VOSI Average Temperature Coefficient Output Offset, VOSO Average Temperature Coefficient Offset Referred to Input vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Average Temperature Coefficient Input Offset Current Average Temperature Coefficient INPUT Input Impedance Differential Common Mode Input Voltage Range 2 Over Temperature Over Temperature Common-Mode Rejection Ratio DC to 60 Hz with 1 k Source Imbalance G=1 G = 10 G = 100 G = 1000 OUTPUT Output Swing Over Temperature VS = 5 V to 18 V Over Temperature Short Current Circuit
Rev. D | Page 3 of 16
Conditions G = 1 + (50.5 k/RG) VOUT = 10 V
Min 1
Typ
Max 1000
Unit
0.05 0.2 0.2 0.2 VOUT = 10 V RL = 10 k RL = 2 k Gain = 1 Gain > 11 Total RTI Error = VOSI + VOSO/G VS = 5 V to 15 V VS = 5 V to 15 V VS = 5 V to 15 V VS = 5 V to 15 V VS = 5 V to 15 V 80 95 110 110 10 10
0.15 0.50 0.50 0.50
% % % % ppm ppm ppm/C ppm/C V V/C V V/C dB dB dB dB
10 -50 60 600 125 1.0 1500 15
100 120 140 140 2.0 3.0 0.7 2.0 5.0 2.5
nA pA/C nA pA/C
10||2 10||2 VS = 2.6 V to 5 V VS = 5 V to 18 V VCM = 0 V to 10 V 66 86 103 103 RL = 10 k VS = 2.6 V to 5 V 78 98 118 118 -VS + 1.9 -VS + 2.1 -VS + 1.9 -VS + 2.1 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.4
G ||pF G||pF V V V V
dB dB dB dB
-VS + 1.1 -VS + 1.4 -VS + 1.2 -VS + 1.6 18
+VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.5
V V V V mA
AD622
Parameter DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.1% G = 1 to 100 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eni Output Voltage Noise, eno RTI, 0.1 Hz to 10 Hz G=1 G = 10 G = 100 Current Noise 0.1 Hz to 10 Hz REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range 3 Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance
1 2
Conditions
Min
Typ
Max
Unit
1000 800 120 12 1.2 10 V step 10 Total RTI Noise = (e2ni) + (enoG)2 12 72 4.0 0.6 0.3 100 10 20 50 -VS + 1.6 1 0.0015 2.6 VS = 2.6 V to 18 V 0.9 1.1 -40 to +85 18 1.3 1.5
kHz kHz kHz kHz V/s s
nV/Hz nV/Hz V p-p V p-p V p-p fA/Hz pA p-p k A V
f = 1 kHz
VIN+, VREF = 0
60 +VS - 1.6
V mA mA C
Does not include effects of External Resistor RG. One input grounded, G = 1. 3 Defined as the same supply range that is used to specify PSR.
Rev. D | Page 4 of 16
AD622 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage Internal Power Dissipation1 Input Voltage (Common Mode) Differential Input Voltage2 Output Short Circuit Duration Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec)
1 2
THERMAL RESISTANCE
Rating 18 V 650 mW VS 25 V Indefinite -65C to +125C -40C to +85C 300C
JA is specified for the device in free air. Table 3. Thermal Resistance
Package Type 8-Lead PDIP (N-8) 8-Lead SOIC_N (R-8) JA 95 155 Unit C/W C/W
ESD CAUTION
Specification is for device in free air; see Table 3. May be further restricted for gains greater than 14. See the Input Protection section for more information.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. D | Page 5 of 16
AD622 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, VS = 15 V, RL = 2 k, unless otherwise noted.
50 SAMPLE SIZE = 191 40
VOLTAGE NOISE (nV/ Hz)
PERCENTAGE OF UNITS
1000
GAIN = 1 100
30
GAIN = 10
20
10 GAIN = 100, 1000 GAIN = 1000 BW LIMIT
10
00777-002
-0.8
-0.4
0
0.4
0.8
1.2
1
10
100
1k
10k
100k
OUTPUT OFFSET VOLTAGE (mV)
FREQUENCY (Hz)
Figure 2. Typical Distribution of Output Offset Voltage
50 SAMPLE SIZE = 383 40
Figure 5. Voltage Noise Spectral Density vs. Frequency (G = 1 to 1000)
1000
30
CURRENT NOISE (fA/ Hz)
PERCENTAGE OF UNITS
100
20
10
00777-003
60
80
100
120
140
1
10
100 FREQUENCY (Hz)
1000
COMMON-MODE REJECTION RATIO (dB)
Figure 3. Typical Distribution of Common-Mode Rejection
2.0 140 120
INPUT OFFSET VOLTAGE (V)
Figure 6. Current Noise Spectral Density vs. Frequency
G = 1000 G = 100 G = 10
1.5
100
CMR (dB)
80 G=1 60 40 20
1.0
0.5
00777-004
0
1
2
3
4
5
1
10
100
1k
10k
100k
1M
WARM-UP TIME (Minutes)
FREQUENCY (Hz)
Figure 4. Change in Input Offset Voltage vs. Warm-Up Time
Figure 7. CMR vs. Frequency, RTI, 0 k to 1 k Source Imbalance
Rev. D | Page 6 of 16
00777-007
0
0 0.1
00777-006
0
10
00777-005
0 -1.2
1
AD622
180 160 140
POSITIVE PSR (dB)
30
VS = 15V G = 10
OUTPUT VOLTAGE SWING (V p-p)
00777-008
120 100 80 60 40 20 0.1
20
G = 1000
G = 100
10
G = 10 G=1 1 10 100 1k 10k 100k 1M
100
1k
10k
FREQUENCY (Hz)
LOAD RESISTANCE ()
Figure 8. Positive PSR vs. Frequency, RTI (G = 1 to 1000)
180 160 140
NEGATIVE PSR (dB)
Figure 11. Output Voltage Swing vs. Load Resistance
20
15
SETTLING TIME (s)
120 100 G = 1000 80 60 40 20 0.1 G = 100 G = 10 G=1
00777-009
TO 0.1% 10
5
1
10
100
1k
10k
100k
1M
0
5
10 OUTPUT STEP SIZE (V)
15
20
FREQUENCY (Hz)
Figure 9. Negative PSR vs. Frequency, RTI (G = 1 to 1000)
1000 1000
Figure 12. Settling Time vs. Step Size (G = 1)
100
SETTLING TIME (s)
100
GAIN (V/V)
10
10
1
00777-010
1k
10k
100k
1M
10M
1
10 GAIN
100
1000
FREQUENCY (Hz)
Figure 10. Gain vs. Frequency
Figure 13. Settling Time to 0.1% vs. Gain, for a 10 V Step
Rev. D | Page 7 of 16
00777-013
0.1 100
1
00777-012
0
00777-011
0 10
AD622
INPUT 20V p-p
100 90
10k 0.01%
1k POT
10k 0.1% VOUT
100k 0.1% +VS 11k 0.1% 1k 0.1%
G = 1000
O
100 0.1%
G=1 G = 100 G = 10
2 1
7
AD622
8 3 4 5
6
0%
00777-014
511
10
5.62k
51.1
10V
2V
Figure 14. Gain Nonlinearity, G = 1, RL = 10 k (20 V = 2 ppm)
Figure 15. Settling Time Test Circuit
Rev. D | Page 8 of 16
00777-015
-VS
AD622 THEORY OF OPERATION
The AD622 is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach. Absolute value trimming allows the user to program gain accurately (to 0.5% at G = 100) with only one resistor. Monolithic construction and laser wafer trimming allow the tight matching and tracking of circuit components, thus insuring AD622 performance. Input Transistor Q1 and Input Transistor Q2 provide a single differential-pair bipolar input for high precision (see Figure 16). Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop maintains constant collector current of the Q1 and Q2 input devices, thereby impressing the input voltage across External Gain-Setting Resistor RG. This creates a differential gain from the inputs to the A1 and A2 outputs given by G = (R1 + R2)/RG + 1. Unity-Gain Subtracter A3 removes any common-mode signal, yielding a single-ended output referred to the REF pin potential. The value of RG also determines the transconductance of the preamp stage. As RG is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors. This has the following three important advantages: * * Open-loop gain is boosted for increasing programmed gain, thus reducing gain-related errors. The gain-bandwidth product (determined by C1, C2, and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. The input voltage noise is reduced to a value of 12 nV/Hz, determined mainly by the collector current and base resistance of the input devices.
*
The internal gain resistors, R1 and R2, are trimmed to an absolute value of 25.25 k, allowing the gain to be programmed accurately with a single external resistor.
I1
20A
VB
20A
I2
MAKE vs. BUY: A TYPICAL APPLICATION ERROR BUDGET
10k
A1 C1
A2 C2 10k
A3 R3 400 R1 Q1 RG GAIN SENSE GAIN SENSE R2 Q2 10k 10k +IN
OUTPUT REF
-IN
R4 400
-VS
Figure 16. Simplified Schematic of the AD622
The AD622 offers cost and performance advantages over discrete two op amp instrumentation amplifier designs along with smaller size and fewer components. In a typical application shown in Figure 17, a gain of 10 is required to receive and amplify a 0 to 20 mA signal from the AD694 current transmitter. The current is converted to a voltage in a 50 shunt. In applications where transmission is over long distances, line impedance can be significant so that differential voltage measurement is essential. Where there is no connection between the ground returns of transmitter and receiver, there must be a dc path from each input to ground, implemented in this case using two 1 k resistors. The error budget detailed in Table 4 shows how to calculate the effect of various error sources on circuit accuracy.
00777-021
RL2 10 0 TO 20mA TRANSMITTER
+ 1k VIN 50 1k RG 5.62k
AD694
0 TO 20mA RL2 10
1/2 LT1013
1k 9k* 1k* 1k*
AD622
REF
-
1/2 LT1013
1k
9k*
*0.1% RESISTOR MATCH, 50ppm/C TRACKING
0 TO 20mA CURRENT LOOP WITH 50 SHUNT IMPEDANCE
AD622 MONOLITHIC INSTRUMENTATION AMPLIFIER, G = 9.986
HOMEBREW IN-AMP, G = 10
Figure 17. Make vs. Buy
Rev. D | Page 9 of 16
00777-016
AD622
The AD622 provides greater accuracy at lower cost. The higher cost of the homebrew circuit is dominated in this case by the matched resistor network. One could also realize a homebrew design using cheaper discrete resistors that are either trimmed or hand selected to give high common-mode rejection. This level of common-mode rejection, however, degrades significantly Table 4. Make vs. Buy Error Budget
Total Error in ppm Relative to 1 V FS AD622 Homebrew 400 2.5 25 427.5 3300 210 0.12 3510.12 10 0.6 10.6 3948 1600 15 50 1665 3000 1080 9.3 4089.3 20 0.778 20.778 5775
over temperature due to the drift mismatch of the discrete resistors. Note that for the homebrew circuit, the LT1013 specification for noise has been multiplied by 2. This is because a two op amp type instrumentation amplifier has two op amps at its inputs, both contributing to the overall noise.
Error Source ABSOLUTE ACCURACY at TA = 25C Total RTI Offset Voltage, V Input Offset Current, nA CMR, dB DRIFT TO 85C Gain Drift, ppm/C Total RTI Offset Voltage, V/C Input Offset Current, pA/C RESOLUTION Gain Nonlinearity, ppm of Full Scale Typ 0.1 Hz to 10 Hz Voltage Noise, V p-p
AD622 Circuit Calculation 250 V + 1500 V/10 2.5 nA x 1 k 86 dB50 ppm x 0.5 V
Homebrew Circuit Calculation 800 V x 2 15 nA x 1 k (0.1% Match x 0.5 V)/10 V Total Absolute Error (50 ppm)/C x 60C 9 V/C x 2 x 60C 155 pA/C x 1 k x 60C Total Drift Error 20 ppm 0.55 V p-p x 2 Total Resolution Error Grand Total Error
(50 ppm + 5 ppm) x 60C (2 V/C + 15 V/C /10) x 60C 2 pA/C x 1 k x 60C
10 ppm 0.6 V p-p
Rev. D | Page 10 of 16
AD622 GAIN SELECTION
The AD622 gain is resistor programmed by RG or, more precisely, by whatever impedance appears between Pin 1 and Pin 8. The AD622 is designed to offer gains as close as possible to popular integer values using standard 1% resistors. Table 5 shows required values of RG for various gains. Note that for G = 1, the RG pins are unconnected (RG = ). For any arbitrary gain, RG can be calculated by using the formula separately. For longer time periods, the input current should not exceed 6 mA. For input overloads beyond the supplies, clamping the inputs to the supplies (using a diode such as a BAV199) reduces the required resistance, yielding lower noise.
Large Input Voltages at Large Gains
When operating at high gain, large differential input voltages may cause more than 6 mA of current to flow into the inputs. This condition occurs when the maximum differential voltage exceeds the following critical voltage: VCRITICAL = (400 + RG) x (6 mA) This is true for differential voltages of either polarity. The maximum allowed differential voltage can be increased by adding an input protection resistor in series with each input. The value of each protection resistor should be as follows: RPROTECT = (VDIFF_MAX - VCRITICAL)/6 mA
RG =
50.5 k G -1
To minimize gain error, avoid high parasitic resistance in series with RG. To minimize gain drift, RG should have a low temperature coefficient less than 10 ppm/C for the best performance. Table 5. Required Values of Gain Resistors
Desired Gain 2 5 10 20 33 40 50 65 100 200 500 1000 1% Std Table Value of RG, 51.1 k 12.7 k 5.62 k 2.67 k 1.58 k 1.3 k 1.02 k 787 511 255 102 51.1 Calculated Gain 1.988 4.976 9.986 19.91 32.96 39.85 50.50 65.17 99.83 199.0 496.1 989.3
RF INTERFERENCE
RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance may appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass, RC network placed at the input of the instrumentation amplifier, as shown in Figure 18. In addition, this RC input network also provides additional input overload protection (see the Input Protection section).
+VS 0.1F R 4.02k R 4.02k CC 1nF CD 47nF CC 1nF 10F +
INPUT AND OUTPUT OFFSET VOLTAGE
The low errors of the AD622 are attributable to two sources: input and output errors. The output error is divided by G when referred to the input. In practice, the input errors dominate at high gains and the output errors dominate at low gains. The total VOS for a given gain is calculated as follows: Total Error RTI = input error + (output error/G) Total Error RTO = (input error x G) + output error
+IN RG -IN
AD622
VOUT REF
0.1F -VS
10F
Figure 18. RFI Suppression Circuit for AD622 Series In-Amps
REFERENCE TERMINAL
The reference terminal potential defines the zero output voltage and is especially useful when the load does not share a precise ground with the rest of the system. The reference terminal provides a direct means of injecting a precise offset to the output, with an allowable range of 2 V within the supply voltages. Parasitic resistance should be kept to a minimum for optimum CMR.
The filter limits the input signal bandwidth to the following cutoff frequencies:
FilterFreq DIFF = FilterFreqCM = where CD 10CC.
1 2 R(2C D + CC )
1 2 RCC
INPUT PROTECTION
The AD622 features 400 of series thin film resistance at its inputs and safely withstands input overloads of up to 15 V or 60 mA for up to an hour at room temperature. This is true for all gains and power on and off, which is particularly important because the signal source and amplifier can be powered
Rev. D | Page 11 of 16
00777-017
+
AD622
Figure 18 shows an example where the differential filter frequency is approximately 400 Hz, and the common-mode filter frequency is approximately 40 kHz. With this differential filter in place and operating at gain of 1000, the typical dc offset shift over a frequency range of 1 Hz to 20 MHz is less than 1.5 V RTI, and the RF signal rejection of the circuit is better than 71 dB. At a gain of 100, the dc offset shift is well below 1 mV RTI, and RF rejection is greater than 70 dB. The input resistors should be selected to be high enough to isolate the sensor from the CC and C D capacitors but low enough not to influence system noise. Mismatch between R x CC at the positive input and R x CC at the negative input degrades the CMRR of the AD622. Therefore, the CC capacitors should be high precision types such as NPO/COG ceramics. The tolerance of the CD capacitor is less critical.
+VS -IN
2 1 7
RG
8
AD622
5 4 3
6
VOUT LOAD
+IN
REF
00777-018
-VS
TO POWER SUPPLY GROUND
Figure 19. Ground Returns for Bias Currents with Transformer Coupled Inputs
+VS -IN
2 1 7
RG
8
AD622
5 4 3
6
VOUT LOAD
GROUND RETURNS FOR INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the input transistors of an amplifier. There must be a direct return path for these currents; therefore, when amplifying floating input sources such as transformers or ac-coupled sources, there must be a dc path from each input to ground as shown in Figure 19, Figure 20, and Figure 21. Refer to the Designer's Guide to Instrumentation Amplifiers (free from Analog Devices, Inc.) for more information regarding in-amp applications.
+IN
REF
00777-019
00777-020
-VS
TO POWER SUPPLY GROUND
Figure 20. Ground Returns for Bias Currents with Thermocouple Inputs
+VS -IN
2 1 7
RG
8
AD622
5 4 3
6
VOUT LOAD
+IN 100k 100k
REF -VS TO POWER SUPPLY GROUND
Figure 21. Ground Returns for Bias Currents with AC-Coupled Inputs
Rev. D | Page 12 of 16
AD622 OUTLINE DIMENSIONS
0.400 (10.16) 0.365 (9.27) 0.355 (9.02)
8 1 5
4
0.280 (7.11) 0.250 (6.35) 0.240 (6.10)
0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14)
0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
0.015 (0.38) MIN SEATING PLANE 0.005 (0.13) MIN
0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX
0.014 (0.36) 0.010 (0.25) 0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 22. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters)
5.00 (0.1968) 4.80 (0.1890)
4.00 (0.1574) 3.80 (0.1497)
8 1
5 4
6.20 (0.2441) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
0.51 (0.0201) 0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 23. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
Rev. D | Page 13 of 16
012407-A
070606-A
AD622
ORDERING GUIDE
Model AD622AN AD622ANZ 1 AD622AR AD622AR-REEL AD622AR-REEL7 AD622ARZ1 AD622ARZ-RL1 AD622ARZ-RL71
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N
Package Option N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8
Z = RoHS Compliant Part.
Rev. D | Page 14 of 16
AD622 NOTES
Rev. D | Page 15 of 16
AD622 NOTES
(c)1996-2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00777-0-8/07(D)
Rev. D | Page 16 of 16

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